1. Field of the Invention
The present invention relates to a memory system included in a digital signal processor or the like.
2. Description of the Related Art
Generally, in a digital signal processor, separate memory spaces are provided for programs and data. Sometimes, however, program memory space runs short, and excess data memory space exists, and it would be desirable to be able to reallocate memory from one to the other. Typically, however, the memory space is completely divided into a program space and a data space. That is, a program memory is connected to only a data bus. Thus, since the program memory and the data memory are completely independent of each other, there is no way to use part of the program memory data memory and vice versa.
In order to permit reallocation between the program memory and the data memory, in one digital signal processor design, the system includes a program bus, a data bus, a large scale memory space and a memory priority sequence controller, so that the user can freely allocate the memory space between the memory spaces for the program bus and the data bus as required. A system of this kind is shown in Japan patent application 63-303452, published Dec. 12, 1988.
In the above-described prior art memory system, however, the program bus has the same bit width as the data bus. However, in some digital signal processors such as the PD7701X family manufactured by NEC Corporation, a program memory having a bit width of 32 bits and two data memories each having a bit width of 16 bits are provided. That is, a program memory space and two data memory spaces are provided. The two data memory spaces are helpful in carrying out pipeline processing Because the program bus and the data bus in these digital signal processors have different bit widths, the memory management scheme shown in Japan published application 63-303452 can not be used. If additional data or program memory is needed, the onboard memory must be increased, or external memory must be provided, which increases the manufacturing cost. In addition, the memory priority sequence controller in the published application dissipates a large amount of power.